This invention relates to the field of output driver or buffer circuits, and more particularly to the field of minimizing crossover impedance fluctuations during state transitions of an output driver circuit having two transmission gates whose active impedances nominally match the circuit or transmission line being driven.
When testing integrated circuit devices or modules, low-distortion input waveforms are required at the input terminals of the device under test (DUT). The input terminals of the DUT and the output driver of the tester are separated by a transmission line which shall be referred to as the tester I/O path. The tester output driver circuit generates waveforms that travel the tester I/O path and provide stimulus to the input terminal of the DUT.
U.S. Pat. No. 4,707,620 describes an adjustable impedance driver network comprising a plurality of CMOS (complementary metal-oxide semiconductor) transmission gates each of which is separately controlled by programmable digital input codes to vary the overall impedance of the network in its conducting state. While this CMOS driver (or buffer) has the advantages of an adjustable output impedance, fast rise times that permit operation up to 100 MHz or more, and relatively low cost, it suffers from the disadvantage of not producing a stable impedance during transitions between logic states.
FIG. 1 is a simplified schematic diagram of a prior art output driver circuit on a CMOS integrated circuit (IC), a tester I/O path external to the IC, and a device under test (DUT). The DUT circuitry may or may not, at any given time, provide a termination resistor to a termination voltage. The circuitry of the output driver includes two CMOS transmission gate networks and an associated control logic circuit. When an Inhibit signal is asserted (high), both CMOS transmission gate networks are held off and the driver is in a high impedance state, effectively disconnected from the tester I/O path. If the driver is not inhibited, a logic "1" on the Data input turns on the upper CMOS transmission gate network and thereby connects the V-high voltage level to the tester I/O path through the nominal impedance of the CMOS transmission gate. When Data is a logic "0", the lower CMOS transmission gate network is turned on and the V-low voltage level is connected to the tester I/O path through the nominal impedance of that CMOS transmission gate.
FIG. 2 is a timing diagram showing how the output impedance of the driver circuitry may vary during logic state transitions due to different propagation delays through the control logic circuitry of FIG. 1. Slight variations between the transition times of the low-enable signal and the high-enable signal can lead to intervals of very high (or too low) impedance on the output. The control circuit shown in FIG. 1 consistently turns off the currently enabled transmission gate before turning on the other one, so the impedance fluctuation is always in the high direction.
Normally, the impedance of the output driver circuitry is approximately matched to the impedance of the tester I/O path. But, during these transition intervals with their very high impedance, a serious impedance mismatch occurs and this can cause problems under some circumstances. In particular, if a reflected voltage wavefront arrives back at the driver during one of these periods, the resulting impedance mismatch causes a strong reflection back toward the DUT and the signal quality is degraded. In other cases, even when the tester I/O path is terminated, those periods when one device has turned off before the other device turns on can cause glitches and other aberrant behavior, depending on the voltage to which the tester I/O path is being terminated.
What is desired is a method and apparatus for minimizing the amount of impedance mismatch that occurs during a transition in logic states in an output driver circuit having two transmission gates whose active impedances nominally match the circuit or transmission line being driven.